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preliminary flex72? 3.3v 64k/128k/256k x 72 synchronous dual-port ram cyd04s72v cyd09s72v cyd18s72v cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-06069 rev. *d revised june 23, 2004 features ? true dual-ported memory cells that allow simultaneous access of the same memory location ? synchronous pipelined operation ? family of 4-mbit, 9-mbit and 18-mbit devices ? pipelined output mode allows fast operation ? 0.18-micron cmos for optimum speed and power ? high-speed clock to data access ? 3.3v low power ? active as low as 225 ma (typ) ? standby as low as 55 ma (typ) ? mailbox function for message passing ? global master reset ? separate byte enables on both ports ? commercial and industrial temperature ranges ? ieee 1149.1-compatible jtag boundary scan ? 484-ball fbga (1 mm pitch) ? counter wrap around control ? internal mask register controls counter wrap-around ? counter-interrupt flags to indicate wrap-around ? memory block retransmit operation ? counter readback on address lines ? mask register readback on address lines ? dual chip enables on both ports for easy depth expansion ? seamless migration to next generation dual port family functional description the flex72 family includes 4-mbit, 9-mbit and 18-mbit pipelined, synchronous, true dual-port static rams that are high-speed, low-power 3.3v cmos. two ports are provided, permitting independent, simultaneous access to any location in memory. the result of writin g to the same location by more than one port at the same ti me is undefined. registers on control, address, and data lines allow for minimal set-up and hold time. during a read operation, data is registered for decreased cycle time. each port contains a burst counter on the input address register. after externally loading the counter with the initial address, the counter will increment the address inter- nally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce0 or low on ce1 for on e clock cycle will power down the internal circuitry to reduce the static power consumption. one cycle with chip enables asserted is required to reactivate the outputs. additional features include: r eadback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (cntint ) flags, readback of mask register value on address lines, retransmit functionality, inte rrupt flags for message passing, jtag for boundary scan, and asynchronous master reset (mrst ). the cyd18s72v device have lim ited features. please see ?address counter and mask register operations [16] ? on page 6 for details. seamless migration to next generation dual port family cypress offers a migration path for all devices to the next-generation devices in the dual-port family with a compatible footprint. please contact cypress sales for more details table 1. product selection guide density 4-mbit (64k x 72) 9-mbit (128k x 72) 18-mbit (256k x 72) part number cyd04s72v cyd09s72v cyd18s72v max. speed (mhz) 167 167 133 max. access time - clock to data (ns) 4.0 4.0 5.0 typical operating current (ma) 225 270 410 package 484-ball fbga 23mm x 23mm 484-ball fbga 23mm x 23mm 484-ball fbga 23mm x 23mm
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 2 of 26 . note: 1. cyd04s72v have 16 address bits, cyd09s72v have 17 address bits and cyd18s72v have 18 bits. logic block diagram [1] ftsel l portst[1:0] l dq[71:0] l be [7:0] l ce 0 l ce1 l oe l r/w l ftsel r portst[1:0] r dq [71:0] r be [7:0] r ce 0 r ce1 r oe r r/w r a [17:0] l cnt/msk l ads l cnten l cntrst l ret l cntint l c l wrp l a [17:0] r cnt/msk r ads r cnten r cntrst r ret r cntint r c r wrp r config block config block io control io control address & counter logic address & counter logic int l trst tms tdi tdo tck jtag mrst ready r lowspd r ready l lowspd l reset logic int r busy l busy r mailboxes arbitration logic dual ported array
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 3 of 26 pin configuration 2. this ball will represent a next generation dual-port feature. fo r more information about this feature, contact cypress sales 3. connect this ball to vddio. for more information about th is next generation dual-port feature contact cypress sales. 4. connect this ball to vss. for more information about this next generation dual-port feature, contact cypress sales. 5. leave this ball unconnected. for more information about this feature, contact cypress sales. 6. leave this ball unconnected for a 64k x 72 configuration. 7. leave this ball unconnected for 128k x 72 and 64k x72 configurations. 8. these balls are not applicable for cyd18s72v device. they need to be tied to vddio. 9. these balls are not applicable for cyd18s72v device. they need to be tied to vss. 10. these balls are not applicable for cyd18s 72v device. they need to be no connected. 484-ball bga top view cyd04s72v / cyd09s72v / cyd18s72v 1 2 3 4 5 6 7 8 9 10 111213 141516171819202122 a nc dq6 1l dq5 9l dq5 7l dq5 4l dq5 1l dq4 8l dq4 5l dq4 2l dq3 9l dq3 6l dq3 6r dq3 9r dq4 2r dq4 5r dq4 8r dq5 1r dq5 4r dq5 7r dq5 9r dq6 1r nc b dq6 3l dq6 2l dq6 0l dq5 8l dq5 5l dq5 2l dq4 9l dq4 6l dq4 3l dq4 0l dq3 7l dq3 7r dq4 0r dq4 3r dq4 6r dq4 9r dq5 2r dq5 5r dq5 8r dq6 0r dq6 2r dq6 3r c dq6 5l dq6 4l vss vss dq5 6l dq5 3l dq5 0l dq4 7l dq4 4l dq4 1l dq3 8l dq3 8r dq4 1r dq4 4r dq4 7r dq5 0r dq5 3r dq5 6r vss vss dq6 4r dq6 5r d dq6 7l dq6 6l vss vss vss nc [2, 5] nc [2, 5] rev l [2,4] low spd l [2,4] por tst d0l [2,4] nc [2, 5] bus y l [2, 5] cnti nt l [10] por tst d1l [2, 5] rev r [2,4] nc [2, 5] nc [2, 5] vss vss vss dq6 6r dq6 7r e dq6 9l dq6 8l vdd iol vss vss vdd iol vdd iol vdd iol vddi ol vddi ol vtt l vtt l vttl vddi or vdd ior vdd ior vdd ior nc vss vdd ior dq6 8r dq6 9r f dq7 1l dq7 0l ce1 l [8] ce 0 l [9] vdd iol vdd iol vdd iol vdd iol vddi ol vco re vco re vco re vco re vddi or vdd ior vdd ior vdd ior vdd ior ce 0 r [9] ce1 r [8] dq7 0r dq7 1r g a0l a1l ret l [2,3] be 4 l vdd iol vdd iol vre fl [2, 4] vss vss vss vss vss vss vss vss vre fr [2, 4] vdd ior vdd ior be 4 r ret r [2,3] a1r a0r h a2l a3l wrp l [2,3] be 5 l vdd iol vdd iol vss vss vss vss vss vss vss vss vss vss vdd ior vdd ior be 5 r wrp r [2,3] a3r a2r j a4l a5l rea dy l [2, 5] be 6 l vdd iol vdd iol vss vss vss vss vss vss vss vss vss vss vdd ior vdd ior be 6 r rea dy r [2, 5] a5r a4r k a6l a7l nc be 7 l vtt l vco re vss vss vss vss vss vss vss vss vss vss vco re vdd ior be 7 r nc a7r a6r l a8l a9l cl oe lvtt l vco re vss vss vss vss vss vss vss vss vss vss vco re vtt l oe rcr a9ra8r m a10l a11l rev l [2,4] be 3 l vtt l vco re vss vss vss vss vss vss vss vss vss vss vco re vtt l be 3 r rev r [2,4] a11 r a10 r n a12l a13l ads l [9] be 2 l vdd iol vco re vss vss vss vss vss vss vss vss vss vss vco re vtt l be 2 r ads r [9] a13 r a12 r p a14l a15l cnt/ msk l [8] be 1 l vdd iol vdd iol vss vss vss vss vss vss vss vss vss vss vdd ior vdd ior be 1 r cnt/ msk r [8] a15 r a14 r r a16l [6] a17l [7] cnt en l [9] be 0 l vdd iol vdd iol vss vss vss vss vss vss vss vss vss vss vdd ior vdd ior be 0 r cnt en r [9] a17 r [7] a16 r [6] t a18l [2,5] nc cnt rst l [8] int lvdd iol vdd iol vre fl [2, 4] vss vss vss vss vss vss vss vss vre fr [2, 4] vdd ior vdd ior int r cnt rst r [8] nc a18 r [2,5] u dq3 5l dq3 4l r/w l rev l [2,4] vdd iol vdd iol vdd iol vdd iol vddi ol vco re vco re vco re vco re vddi or vdd ior vdd ior vdd ior vdd ior rev r [2,4] r/w r dq3 4r dq3 5r v dq3 3l dq3 2l fts el l [2,3] vdd iol nc vdd iol vdd iol vdd iol vddi ol vttl vtt l vtt l vddi or vddi or vdd ior vdd ior vdd ior trs t [2, 5] vdd ior fts el r [2,3] dq3 2r dq3 3r w dq3 1l dq3 0l vss mrs t vss nc [2, 5] nc [2, 5] rev l [2,4] por tst d1r [2, 5] cnti nt r [10] bus y r [2, 5] nc [2, 5] por tst d0r [2,4] low spd r [2,4] rev r [2,4] nc [2, 5] nc [2, 5] vss tdi tdo dq3 0r dq3 1r y dq2 9l dq2 8l vss vss dq2 0l dq1 7l dq1 4l dq1 1l dq8 l dq5 l dq2 l dq2 r dq5 r dq8 r dq1 1r dq1 4r dq1 7r dq2 0r tms tck dq2 8r dq2 9r a a dq2 7l dq2 6l dq2 4l dq2 2l dq1 9l dq1 6l dq1 3l dq1 0l dq7 l dq4 l dq1 l dq1 r dq4 r dq7 r dq1 0r dq1 3r dq1 6r dq1 9r dq2 2r dq2 4r dq2 6r dq2 7r a b nc dq2 5l dq2 3l dq2 1l dq1 8l dq1 5l dq1 2l dq9 l dq6 l dq3 l dq0 l dq0 r dq3 r dq6 r dq9 r dq1 2r dq1 5r dq1 8r dq2 1r dq2 3r dq2 5r nc
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 4 of 26 pin definitions left port right port description a 0l ?a 17l a 0r ?a 17r address inputs . be 0l ?be 7l be 0r ?be 7r byte enable inputs . asserting these signals enables read and write opera- tions to the corresponding bytes of the memory array. busy l [2,5] busy r [2,5] port busy output . when the collision is detected, a busy is asserted. c l c r input clock signal . ce0 l [9] ce0 r [9] active low chip enable input . ce1 l [8] ce1 r [8] active high chip enable input . dq 0l ?dq 71l dq 0r ?dq 71r data bus input/output . oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrupt flag output . the mailbox permits communications between ports. the upper two memory locations can be used for message passing. int l is asserted low when the right port writes to the mailbox location of the left port, and vice versa. an inte rrupt to a port is deasserted high when it reads the contents of its mailbox. lowspd l [2,4] lowspd r [2,4] port low speed select input . when operating at less than 100 mhz, the lowspd disables the port dll. portstd[1:0] l [2,4,5] portstd[1:0] r [2,4,5] port address/control/data i/o standard select input . r/w l r/w r read/write enable input . assert this pin low to write to, or high to read from the dual port memory array. ready l [2,5] ready r [2,5] port ready output . this signal will be asserted when a port is ready for normal operation. cnt/msk l [8] cnt/msk r [8] port counter/mask select input . counter control input. ads l [9] ads r [9] port counter address load strobe input . counter control input. cnten l [9] cnten r [9] port counter enable input . counter control input. cntrst l [8] cntrst r [8] port counter reset input . counter control input. cntint l [10] cntint r [10] port counter interrupt output . this pin is asserted low when the unmasked portion of the counter is incremented to all ?1s?. wrp l [2,3] wrp r [2,3] port counter wrap input . after the burst counter reaches the maximum count, if wrp is low, the unmasked counter bits wi ll be set to 0. if high, the counter will be loaded with the value stored in the mirror register. ret l [2,3] ret r [2,3] port counter retransmit input . counter control input. ftsel l [2,3] ftsel r [2,3] flow-through select . use this pin to select flow-through mode. when is de-asserted, the device is in pipelined mode. vref l [2,5] vref r [2,5] port external high-speed io reference input . vddio l vddio r port io power supply . rev [2,4] l rev [2,4] r reserved pins for future features . mrst master reset input . mrst is an asynchronous input signal and affects both ports. a master reset operation is required at power-up. trst [2,5] jtag reset input . tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 5 of 26 master reset the flex72 family devices undergo a complete reset by taking the mrst input low. mrst input can switch asynchronously to the clocks. mrst initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). mrst also forces the mailbox interrupt (int ) flags and the counter interrupt (cntint ) flags high. mrst must be performed on the flex72 family devices after power-up. mailbox interrupts the upper two memory locations may be used for message passing and permit communications between ports. ta ble 2 shows the interrupt operation for both ports using 18mbit device as an example. the highest memory location, 3ffff is the mailbox for the right port and 3fffe is the mailbox for the left port. table 2. shows that in order to set the int r flag, a write operation by the left port to address 3ffff will assert int r low. at least one byte has to be active for a write to generate an interrupt. a valid read of the 3ffff location by the right port will reset int r high. at least one byte has to be active in order for a read to reset the interrupt. when one port writes to the other port?s mailbox, the int of the port that the mailbox belongs to is asserted low. the int is reset when the owner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-thru mode (i.e., it follow s the clock edge of the writing port). also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). each port can read the other port?s mailbox without resetting the interrupt. and each port can write to its own mailbox without setting the interrupt. if an application does not require message passing, int pins should be left open. tdi jtag test data input . data on the tdi input will be shifted serially into selected registers. tck jtag test clock input . tdo jtag test data output . tdo transitions occur on the falling edge of tck. tdo is normally three-stated except when captured data is shifted out of the jtag tap. v ss ground inputs . v core core power supply . v ttl lvttl power supply . pin definitions (continued) left port right port description table 2. interrupt operation example [1, 11, 12, 13] function left port right port r/w l ce l a 0 l ?17 l int l r/w r ce r a 0r?17r int r set right int r flagl l3ffffxxxxl reset right int r flagxxxxhl3ffffh set left int l flagxxxlll3fffex reset left int l flaghl3fffehxxxx note: 11. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data will be out after the following clk edge and will be three-stated after the next clk edge. 12. oe is ?don?t care? for mailbox operation. 13. at least one of be0 or be7 must be low.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 6 of 26 address counter and mask register operations [16] this section describes the f eatures only apply to 4mbit and 9mbit devices, not to 18mbit device. each port have a programmable burst address counter. the burst counter contains three registers: a co unter register, a mask register, and a mirror register. the counter register contains the address used to access the ram array. it is changed only by the counter load, increment, counter reset, and by master reset (mrst ) operations. the mask register value affects the increment and counter reset operations by preventing the corresponding bits of the counter register from changing. it also affects the counter interrupt output (cntint ). the mask register is changed only by the mask load and mask reset operations, and by the mrst . the mask register defines the counting range of the counter register. it divides the counter register into two regions: zero or more ?0s? in the most significant bits define the masked region, one or more ?1s? in the least significant bits define the unmasked region. bit 0 may also be ?0,? masking the least significant counter bit and causing the counter to increment by two instead of one. the mirror register is used to reload the counter register on increment operations (see ?retransmit,? below). it always contains the value last loaded into the counter register, and is changed only by the counter load, and counter reset opera- tions, and by the mrst . table 3 summarizes the operation of these registers and the required input control signals. the mrst control signal is asynchronous. all the other control signals in ta ble 3 (cnt/msk , cntrst , ads , cnten ) are synchronized to the port?s clk. all these counter and mask operations are independent of the port?s chip enable inputs (ce0 and ce1) counter enable (cnten ) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. a port?s burst counter is loaded when the port?s address strobe (ads ) and cnten signals are low. when the port?s cnten is asserted and the ads is deasserted, the address counter will incr ement on each low to high transition of that port?s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array, and will loop back to the start. counter reset (cntrst ) is used to reset the unmasked portion of the burst counter to 0s. a counter-mask register is used to control the counter wrap. counter reset operation all unmasked bits of the counter and mirror registers are reset to ?0.? all masked bits remain unchanged. a mask reset followed by a counter reset will reset the counter and mirror registers to 00000, as will master reset (mrst ). counter load operation the address counter and mirror registers are both loaded with the address value presented at the address lines. counter increment operation once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addr essing the entire memory array. only the unmasked bits of the counter register are incre- mented. the corresponding bit in the mask register must be a ?1? for a counter bit to change. the counter register is incre- mented by 1 if the least signifi cant bit is unmasked, and by 2 if it is masked. if all unmasked bits are ?1,? the next increment table 3. address counter and counter mask register control operation (any port) [14,15 ] clk mrst cnt/msk cntrst ads cnten operation description x l x x x x master reset reset address counter to all 0s and mask register to all 1s. h h l x x counter reset reset counter unmasked portion to all 0s. h h h l l counter load load counter with external address value presented on address lines. h h h l h counter readback read out counter internal value on address lines. h h h h l counter increment internally increment address counter value. h h h h h counter hold constantly hold the address value for multiple clock cycles. h l l x x mask reset reset mask register to all 1s. h l h l l mask load load mask register with value presented on the address lines. h l h l h mask readback read out mask register value on address lines. h l h h x reserved operation undefined note: 14. x? = ?don?t care,? ?h? = high, ?l? = low. 15. counter operation and mask register operation is independent of chip enables.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 7 of 26 will wrap the counter back to the initially loaded value. if an increment results in all the unmasked bits of the counter being ?1s,? a counter interrupt flag (cntint ) is asserted. the next increment will return the counter register to its initial value, which was stored in the mirro r register. the counter address can instead be forced to loop to 00000 by externally connecting cntint to cntrst . [17] an increment that results in one or more of the unmasked bits of the counter being ?0? will de-assert the counter interrupt flag. the example in figure 2 shows the counter mask register loaded with a mask value of 0003fh unmasking the first 6 bits with bit ?0? as the lsb and bit ?16? as the msb. the maximum value the mask register can be loaded with is 1ffffh. setting the mask register to this value allows the counter to access the entire memory space. the address counter is then loaded with an initial value of 8h. the base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. the counter address will start at address 8h. the counter will increment its internal address value till it reaches the mask register val ue of 3fh. the counter wraps around the memory block to location 8h at the next count. cntint is issued when the counter reaches its maximum value. counter hold operation the value of all three register s can be constantly maintained unchanged for an unlimited number of clock cycles. such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. counter interrupt the counter interrupt (cntint ) is asserted low when an increment operation results in the unmasked portion of the counter register being all ?1s.? it is deasserted high when an increment operation results in any other value. it is also de-asserted by counter reset, counter load, mask reset and mask load operations, and by mrst . counter readback operation the internal value of the counte r register can be read out on the address lines. readback is pipelined; the address will be valid t ca2 after the next rising edge of the port?s clock. if address readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. retransmit retransmit is a feature that allows the read of a block of memory more than once without the need to reload the initial address. this eliminates the need for external logic to store and route data. it also reduces the complexity of the system design and saves board space. an internal ?mirror register? is used to store the initially loaded address counter value. when the counter unmasked portion reaches its maximum value set by the mask register, it wraps ba ck to the initial value stored in this ?mirror register.? if the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the ?mirror register.? thus, the repeated access of the same data is allowed without the need for any external logic. mask reset operation the mask register is reset to all ?1s,? which unmasks every bit of the counter. master reset (mrst ) also resets the mask register to all ?1s.? mask load operation the mask register is loaded with the address value presented at the address lines. not all values permit correct increment operations. permitted values are of the form 2 n ? 1 or 2 n ? 2. from the most significant bit to the least significant bit, permitted values have zero or more ?0s,? one or more ?1s,? or one ?0.? thus 1ffff, 003fe, and 00001 are permitted values, but 1f0ff, 003fc, and 00000 are not. mask readback operation the internal value of the mask register can be read out on the address lines. readback is pipelined; the address will be valid t cm2 after the next rising edge of the port?s clock. if mask readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. counting by two when the least significant bit of the mask register is ?0,? the counter increments by two. this may be used to connect the x72 devices as a 144-bit single port sram in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. this even-odd address scheme stores one half of t he 144-bit data in even memory locations, and the other half in odd memory locations. notes: 16. the cyd04s72v has 16 address bits and a maximum address value of ffff. the cyd09s72v has 17 address bits and a maximum addre ss value of 1ffff. the cyd18s72v has 18 address bits and a maximum address value of 3ffff. 17. cntint and cntrst specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 8 of 26 from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to counter bit 0 wrap figure 1. counter, mask, and mirror logic block diagram [1] 17 17 17 17 17 1 0 load/increment cnt/msk cnten ads cntrst clk decode logic bidirectional address lines mask register counter/ address register from address lines to readback and address decode 17 17 mrst
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 9 of 26 ieee 1149.1 serial boundary scan (jtag) [19] the flex72 incorporates an ieee 1149.1 serial boundary scan test access port (tap). the tap controller functions in a manner that does not conflic t with the operation of other devices using 1149.1-compliant taps. the tap operates using jedec-standard 3.3v i/o l ogic levels. it is composed of three input connections and one output connection required by the test logic defined by the standard. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the flex72 family and may be performed while the device is operating. an mrst must be performed on the flex72 after power-up. performing a pause/restart when a shift-dr pause-dr shift-dr is performed the scan chain will output the next bit in the chain twice. for example, if the value expected from the chain is 1010101, the device will output a 11010101. this extra bit will cause some testers to report an erroneous failure for the flex72 in a scan test. therefore the tester should be configured to never enter the pause-dr state. boundary scan hierarchy for flex72 family internally, the cyd04s72v and cyd09s72v have two dies while cyd18s72v have four dies. each die contains all the circuitry required to support boundary scan testing. the circuitry includes the tap, tap controller, instruction register, and data registers. the circui ty and operation of the die boundary scan are described in detail below. the scan chain of each die is connected serially to form the scan chain of the flex72 family as shown in figure 3 . tms and tck are connected in parallel to each die to drive all 4 tap controllers in unison. in many cases, each die will be supplied with the same instruction. in other cases, it might be useful to supply different instructions to eac h die. one example would be testing the device id of one die while bypassing the others. each pin of flex72 family is typically connected to multiple dies. for connectivity testing with the extest instruction, it is desirable to check the internal connections between dies as well as the external connections to the package. this can be accomplished by merging the netlist of the devices with the netlist of the user?s circuit board. to facilitate boundary scan testing of the devices, cypress provides the bsdl file for each die, the internal netlist of the device, and a description of the device scan chain. the user can use these materials to easily integrate the devices into the board?s boundary scan environment. further information can be found in the cypress application note using jtag boundary scan for system in a package (sip) dual-port srams . 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 01 00 xs 1 x 0 x 0 x0 11 xs 1 x 1 x 1 x1 00 xs 1 x 0 x 0 x0 masked address unmasked address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register figure 2. programmable counter-mask register operation [1, 18] notes: 18. the ?x? in this diagram represents the counter upper bits. 19. boundary scan is ieee 1149.1-compatible. see ?performing a pause/restart? for deviation from strict 1149.1 compliance.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 10 of 26 table 4. identification register definitions instruction field value description revision number(31:28) 0h reserved for version number cypress device(27:12) c002h defines cypress die number for cyd18s72v and cyd09s72v. c001h defines cypress die number for cyd04s72v cypress jdec id(11:1) 034h allows unique identification of flex72 family device vendor id register presence (0) 1 indicates the presence of an id register table 5. scan registers sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [20] table 6. instruction identification codes instruction code description extest 0000 captures the input/out put ring contents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places t he register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces al l flex72 output drivers to a high-z state. clamp 0100 controls boundary to 1/0. places byr between tdi and tdo. sample/preload 1000 captures the input/output ring contents. places bsr between tdi and tdo. nbsrst 1100 resets the non-boundary scan logic. places byr between tdi and tdo. reserved all other codes other comb inations are reserved. do no t use other t han the above. note: 20. see details in the device bsdl files tdo d2 tdi tdo d1 tdi tdo d4 tdi tdo d3 tdi tdo tdi tdo d2 tdi tdo d1 tdi tdi tdo figure 3. scan chain 18 mbit 4 mbit/9 mbit
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 11 of 26 maximum ratings [21] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................ ?65 c to + 150 c ambient temperature with power applied............................................?55 c to + 125 c supply voltage to ground potential .............. ?0.5v to + 4.6v dc voltage applied to outputs in high-z state..........................?0.5v to v dd + 0.5v dc input voltage ............ .................. ?0.5v to v dd + 0.5v [22] output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ...... > 2000v (jedec jesd22-a114-2000b) latch-up current.......... .............. .............. ............... > 200 ma operating range range ambient temperature v dd v core commercial 0 c to +70 c 3.3v 165 mv 1.8v 100 mv industrial ?40 c to +85 c 3.3v 165 mv 1.8v 100mv electrical characteristics over the operating range parameter description part no. -167 -133 -100 unit min. typ. max. min. typ. max. min. typ max v oh output high voltage (v dd = min., i oh = ?4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v dd = min., i ol = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 -10 10 a i ix1 input leakage current except tdi, tms, mrst ?10 10 ?10 10 -10 10 a i ix2 input leakage current tdi, tms, mrst ?0.1 1.0 ?0.1 1.0 -0.1 1.0 ma i cc operating current (v dd = max.,i out = 0 ma), outputs disabled cyd04s72v cyd09s72v 225 300 225 300 ma cyd18s72v 410 580 315 450 ma i sb1 standby current (both ports ttl level) ce l and ce r v ih , f = f max cyd04s72v cyd09s72v 90 115 90 115 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max cyd04s72v cyd09s72v 160 210 160 210 ma i sb3 standby current (both ports cmos level) ce l and ce r v dd ? 0.2v, f = 0 cyd04s72v cyd09s72v 55 75 55 75 ma i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max cyd04s72v cyd09s72v 160 210 160 210 ma i sb5 operating current (vddio = max,iout=0ma,f=0) outputs disabled cyd18s72v 75 75 ma i core core operating current for (v dd = max.,i out = 0 ma), outputs disabled 00 00 0 0ma capacitance [23] part# parameter description test conditions max. unit cyd04s72v cyd09s72v c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v 20 pf c out output capacitance 10 [24] pf cyd18s72v c in input capacitance 40 pf c out output capacitance 20 pf note: 21. the voltage on any input or i/o pin can not exceed the power pin during power-up. 22. pulse width < 20 ns. 23. c out also references c i/o
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 12 of 26 ac test load and waveforms switching characteristics over the operating range parameter description -167 -133 -100 unit cyd04s72v cyd09s72v cyd04s72v cyd09s72v cyd18s72v cyd18s72v min. max. min. max. min. max min. max f max2 maximum operating frequency 167 133 133 100 mhz t cyc2 clock cycle time 6.0 7.5 7.5 10 ns t ch2 clock high time 2.7 3.0 3.4 4.5 ns t cl2 clock low time 2.7 3.0 3.4 4.5 ns t r [25] clock rise time 2.0 2.0 2.0 3.0 ns t f [25] clock fall time 2.0 2.0 2.0 3.0 ns t sa address set-up time 2.3 2.5 2.2 2.7 ns t ha address hold time 0.6 0.6 1.0 1.0 ns t sb byte select set-up time 2.3 2.5 2.2 2.7 ns t hb byte select hold time 0.6 0.6 1.0 1.0 ns t sc chip enable set-up time 2.3 2.5 na na ns t hc chip enable hold time 0.6 0.6 na na ns t sw r/w set-up time 2.3 2.5 2.2 2.7 ns t hw r/w hold time 0.6 0.6 1.0 1.0 ns t sd input data set-up time 2.3 2.5 2.2 2.7 ns t hd input data hold time 0.6 0.6 1.0 1.0 ns t sad ads set-up time 2.3 2.5 na na ns t had ads hold time 0.6 0.6 na na ns t scn cnten set-up time 2.3 2.5 na na ns t hcn cnten hold time 0.6 0.6 na na ns t srst cntrst set-up time 2.3 2.5 na na ns r1 = 590 ? r2 = 435 ? c = 5 pf (b) three-state delay (load 2) 90% 10% 3.0v vss 90% 10% <2ns <2ns all input pulses 3.3v v th = 1.5v r = 50 ? z 0 = 50 ? (a) normal load (load 1) c = 10 pf output output
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 13 of 26 t hrst cntrst hold time 0.6 0.6 na na ns t scm cnt/msk set-up time 2.3 2.5 na na ns t hcm cnt/msk hold time 0.6 0.6 na na ns t oe output enable to data valid 4.0 4.4 5.5 5.5 ns t olz [26, 27] oe to low z 0 0 0 0 ns t ohz [26, 27] oe to high z 0 4.0 0 4.4 0 5.5 0 5.5 ns t cd2 clock to data valid 4.0 4.4 5.0 5.2 ns t ca2 clock to counter address valid 4.0 4.4 na na ns t cm2 clock to mask register readback valid 4.0 4.4 na na ns t dc data output hold after clock high 1.01.01.01.0 ns t ckhz [26, 27] clock high to output high z 0 4.0 0 4.4 0 4.7 0 5.0 ns t cklz [26, 27] clock high to output low z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns t sint clock to int set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns t rint clock to int reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns t scint clock to cntint set time 0.5 5.0 0.5 5.7 na na na na ns t rcint clock to cntint reset time 0.5 5.0 0.5 5.7 na na na na ns port to port delays t ccs clock to clock skew 5.2 6.0 5.7 8.0 ns master reset timing t rs master reset pulse width 5.0 5.0 5.0 5.0 cycles t rss master reset set-up time 6.0 6.0 6.0 8.5 ns t rsr master reset recovery time 5.0 5.0 5.0 5.0 cycles t rsf master reset to outputs inactive 10.0 10.0 10.0 10.0 ns t rscntint master reset to counter interrupt flag reset time 10.0 10.0 na na ns notes: 24. except int and cntint which are 20pf 25. except jtag signal (tr and tf < 10ns max) 26. this parameter is guaranteed by design, but is not production tested 27. test conditions used are load 2 switching characteristics over the operatin g range (continued) parameter description -167 -133 -100 unit cyd04s72v cyd09s72v cyd04s72v cyd09s72v cyd18s72v cyd18s72v min. max. min. max. min. max min. max
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 14 of 26 jtag timing characteristics parameter description cyd04s72v cyd09s72v cyd18s72v unit -167/-133/-100 min. max. f jtag maximum jtag tap controller frequency 10 mhz t tcyc tck clock cycle time 100 ns t th tck clock high time 40 ns t tl tck clock low time 40 ns t tmss tms set-up to tck clock rise 10 ns t tmsh tms hold after tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t tdih tdi hold after tck clock rise 10 ns t tdov tck clock low to tdo valid 30 ns t tdox tck clock low to tdo invalid 0 ns switching waveforms test clock test mode select tck tms test data-in tdi te s t d a ta - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 15 of 26 master reset read cycle [11, 28, 29, 30, 31] notes: 28. oe is asynchronously controlled; all other inputs (excluding mrst and jtag) are synchronous to the rising clock edge. 29. ads = cnten = low, and mrst = cntrst = cnt/msk = high. 30. the output is disabled (high-impedance state) by ce = v ih following the next rising edge of the clock. 31. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. switching waveforms (continued) mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency be0 ?be7 t sb t hb
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 16 of 26 bank select read [32, 33] read-to-write -to-read (oe = low) [31, 34, 35, 36, 37] notes: 32. in this depth-expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress flex72 device fr om this data sheet. address (b1) = address (b2) . 33. ads = cnten = be0 ? be7 = oe = low; mrst = cntrst = cnt/msk = high. 34. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 35. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 36. ce 0 = oe = be0 ? be7 = low; ce 1 = r/w = cntrst = mrst = high. 37. ce 0 = be0 ? be7 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, since oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three- state the i/o for the wr ite operation on the next ri sing edge of clk. switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) clk ce r/w address data in data out t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t ckhz t sd t hd no operation write read a n a n+1 a n+2 a n+2 d n+2 a n+2 a n+3 q n t cl2 t ch2 t cyc2 t dc
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 17 of 26 read-to-write -to-read (oe controlled) [31, 34, 36, 37] read with address counter advance [36] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe q n+4 t cd2 t sa t ha t ch2 t cl2 t cyc2 clk address a n counter hold read with counter t sad t had t scn t hcn t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address ads cnten data out
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 18 of 26 write with address counter advance [37] switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal data in address t sa t ha cnten ads
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 19 of 26 counter reset [38, 39] notes: 38. ce 0 = be0 ? be7 = low; ce 1 = mrst = cnt/msk = high. 39. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [51] reset address 0 counter write read address 0 address 1 read read address a n address a m read
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 20 of 26 readback state of address counter or mask register [40, 41, 42, 43] notes: 40. ce 0 = oe = be0 ? be7 = low; ce 1 = r/w = cntrst = mrst = high. 41. address in output mode. host must not be driving address bus after t cklz in next clock cycle. 42. address in input mode. host can drive address bus after t ckhz . 43. an * is the internal value of the address counter (or the mask register depending on the cnt/msk level) being read out on the address lines. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n t sa t ha t sad t had t scn t hcn load address external t cd2 internal address a n+1 a n+2 a n t ckhz data out a n* q n+3 q n+1 q n+2 a n+3 a n+4 t cklz t ca2 or t cm2 readback internal counter address increment external a 0 ?a 17
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 21 of 26 left_port (l_port) write to right_port (r_port) read [44, 45, 46] notes: 44. ce 0 = oe = ads = cnten = be0 ? be7 = low; ce 1 = cntrst = mrst = cnt/msk = high. 45. this timing is valid when one port is writing, and other port is reading the same location at the same time. if t ccs is violated, indeterm inate data will be read out. 46. if t ccs < minimum specified value, then r_po rt will read the most recent data (written by l_port) only (2 * t cyc2 + t cd2 ) after the rising edge of r_port's clock. if t ccs > minimum specified value, then r_port will read the most recent data (written by l_port) (t cyc2 + t cd2 ) after the rising edge of r_port's clock. switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk l r/w l a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 l_port address l_port data in clk r r/w r r_port address r_port data out
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 22 of 26 counter interrup t and retransmit [47, 48, 49, 50, 51] notes: 47. ce 0 = oe = be0 ? be7 = low; ce 1 = r/w = cntrst = mrst = high. 48. cntint is always driven. 49. cntint goes low when the unmasked portion of the address counter is incremented to the maximum value. 50. the mask register assumed to have the value of 1ffffh. 51. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. switching waveforms (continued) t ch2 t cl2 t cyc2 clk 1fffd 1ffff internal address last_loaded last_loaded +1 t hcm counter 1fffe cntint t scint t rcint 1fffc cnten ads cnt/msk t scm
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 23 of 26 mailbox interrupt timing [52,53,54,55,56] table 7. read / write and enable operation (any port) [1,14,57,58,59] inputs outputs operation oe clk ce 0 ce 1 r/w dq 0 ? dq 71 x h x x high-z deselected x x l x high-z deselected xlhld in write llhhd out read h x l h x high-z outputs disabled notes: 52. ce 0 = oe = ads = cnten = low; ce 1 = cntrst = mrst = cnt/msk = high. 53. address ?1ffff? is the mailbox location for r_port. 54. l_port is configured for write operation, and r_port is configured for read operation. 55. at least one byte enable (b0 ? b3 ) is required to be active during interrupt operations. 56. interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of th e read clock. 57. oe is an asynchronous input signal. 58. when ce changes state, deselection and read happen after one cycle of latency. 59. ce 0 = oe = low; ce 1 = r/w = high. t ch2 t cl2 t cyc2 clk l t ch2 t cl2 t cyc2 clk r 3ffff t sa t ha a n+3 a n a n+1 a n+2 l_port address a m a m+4 a m+1 3ffff a m+3 r_port address int r t sa t ha t sint t rint
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 24 of 26 ordering information 256k 72 (18mb) 3.3v synchronous cyd18s72v dual-port sram speed (mhz) ordering code package name package type operating range 133 cyd18s72v-133bbc bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial 100 cyd18s72v-100bbc bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial cyd18s72v-100bbi bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) industrial 128k 72 (9mb) 3.3v synchronous cyd09s72v dual-port sram 167 cyd09s72v-167bbc bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial 133 cyd09s72v-133bbc bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial cyd09s72v-133bbi bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) industrial 64k x 72 (4mb) 3.3 synchronous cyd04s72v dual-port sram 167 cyd04s72v-167bbc bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial 133 CYD04S72V-133BBC bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) commercial cyd04s72v-133bbi bb484 484-ball grid array 23mm x 23mm with 1.0mm pitch (fbga) industrial
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 25 of 26 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram 484-ball fbga (23 mm 23 mm 1.9 mm) bb484 51-85124-*d flex72 is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders.
preliminary cyd04s72v cyd09s72v cyd18s72v document #: 38-06069 rev. *d page 26 of 26 document history page document title: flex72? 3.3v 64k/128 k/256k x 72 synchronous dual-port ram document number: 38-06069 rev. ecn no. issue date orig. of change description of change ** 125859 06/17/03 spn new data sheet *a 128707 08/01/03 spn added -133 speed bin updated spec values for i cc, t ha, t hb, t hw, t hd added new parameter i cc1 added bank select read and read to write to read (oe =low) timing diagrams *b 128997 09/18/03 spn updated spec values for t oe, t ohz, t ch2, t cl2, t ha, t hb, t hw, t hd, i cc, i sb5, t sa, t sb, t sw, t sd, t cd2 updated read to write (oe =low) timing diagram updated master reset values for t rs, t rsr, t rsf updated pinout updated v core voltage range *c 129936 09/30/03 spn updated package diagram updated t cd2 value on first page removed preliminary status *d 233830 see ecn wwz added 4m and 9m x72 devices into the datasheet with updated pinout, pin description table, power table, and timing table. changed the title and added back preliminary status to reflect the addition of 4m and 9m devices. removed flex72-e word from the document. added counter related functions for 4m and 9m. removed standard jtag description. updated block diagram. updated pinout with ftsel and one more portstd pins per port. updated trsf of cyd18s72v value.

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